B.S. in Computer Engineering · The College of New Jersey, 2026
Sofia Francesca Cecilia Hall
Hi! I'm Sofia, a recent Computer Engineering graduate from The College of New Jersey. My work spans software and hardware. Learn more about me below!
Conrad Johnson Award, 2026For outstanding craftsmanship in a senior design project. My group and I built an autonomous wheelchair; as ROS lead, I led the simulation and autonomous navigation.
I currently work part-time as a Software and Systems Engineer at Atrevida Science, and I'm looking for a full-time engineering role.
Outside of work I like to stay active. I swam competitively for my school's NCAA Division III team, and I've coached swimming since. I like hiking, cycling, and pretty much anything that gets me outside, and I travel whenever I get the chance.
Fun fact about me: I have lived in five different states!
Projects
Autonomous Wheelchair
Conrad Johnson Award
Senior design capstone · Feb 2025 – May 2026 · ROS lead
My group built an autonomous wheelchair. As ROS lead I owned the simulation and autonomous navigation: Python launch files for localization and navigation, a custom simulation environment, URDF robot models, and LiDAR-based obstacle avoidance, kept in step with changes to the physical platform. More than 100 rounds of simulation and hardware testing, and the Conrad Johnson Award for outstanding craftsmanship in a senior design project.
LiDAR in the Gazebo simulation picking up an obstacle and the walls within 12 m.The room as the wheelchair mapped it.The wheelchair navigating autonomously while avoiding obstacles in the room.
A ROS 2 simulation of adaptive wind-turbine blade mechanisms, modeled in URDF and driven by Python launch files, with scenario tests for wind gusts, low wind, and communication disruptions. Results and error logs go to SQLite, where I use SQL and pandas to compare runs and find unexpected behavior. Ongoing work.
ROS 2
URDF
Python
SQLite
SQL
pandas
Pipelined ARM Processor
Sep 2025 · Computer architecture
A pipelined ARM processor in SystemVerilog with separate instruction and data memories, implementing a subset of the ARM instruction set, then extended with forwarding and hazard detection. Verified with ARM assembly test programs and simulation waveforms in Vivado.
A memory write cycle.
SystemVerilog
ARM assembly
Xilinx Vivado
Embedded Temperature Controller
May 2023 · Arduino Nano RP2040
Proportional control of a resistive heater: filtered ADC temperature readings, a 1 kHz PWM output, and a live readout on an I2C OLED. I swept the gain from 100 to 10⁶ and held temperature within about ±1 °C of the setpoint.
C++
Proportional control
ADC
PWM
I2C
Cache Simulator
Oct 2025 · Computer architecture
A configurable, trace-driven cache simulator in C++ with FIFO and LRU replacement. I compared 32 runs across two traces, varying size and associativity, and documented the effect on hit rate. A SystemVerilog version was verified on the same traces.
C++
SystemVerilog
FIFO & LRU
UNIX Shell
Mar 2026 · Systems programming · Linux
A command-line shell with fork/execvp process creation, pipes, dup2 redirection, and a command history with !! and arrow-key navigation using termios.
C
fork / execvp
pipes
dup2
termios
More projects
FIR Filter Design
Mar 2026 · MATLAB
Equiripple lowpass and highpass filters, tested on a ten-component signal at 1 kHz and combined into one system.
Inverted Pendulum Control
Oct 2025 · MATLAB, Simulink, Quanser
Balance and swing-up controllers compared against simulation, plus PID tuning for a mass–spring–damper system.
PLC Traffic-Signal Controller
Dec 2024 · Do-More PLC
State diagrams implemented in ladder logic with timers, counters, and function blocks; six outputs verified in simulation.
PSoC 5LP Firmware Labs
Fall 2024 · C
GPIO, keypad scanning, LCD output, debouncing, memory-mapped registers, and ADC/DAC conversion checked against measured voltages.
Analog Circuit Labs
May 2024 · PSpice, oscilloscope
An op-amp summing circuit, a rectifier/filter/Zener supply with ripple measured under load, and MOSFET switching and amplifier circuits.
Predator–Prey Simulator
May 2024 · Java · team
A wolves, sheep, and grass ecosystem with shared Animal behavior and timer-driven movement, feeding, and reproduction.
Swim-Time Predictor In progress
2026 · Python, NumPy, SQLite
Monte Carlo estimates of a swimmer's future times, shown as a range rather than one number.
Research and Modeling
HPetriSim
Wireless sensor nodes for solar-energy applications, and discrete-event simulations in HPetriSim.
Lab coursework
Computer architecture and FPGA: 64-bit adders, a 16-bit accumulator processor, a single-cycle ARM processor with added instructions, an ARM cache, and FPGA projects on the Nexys4 DDR.
Digital signal processing: frequency analysis, sampling and reconstruction, DFT/FFT convolution, and Butterworth IIR design in MATLAB and Python.
VLSI design (Cadence): CMOS gate design and layout, D flip-flop characterization, and charge-pump PLL building blocks.
